Dielectric waveguide filter

ABSTRACT

A conductive layer is formed on each of the upper and lower surfaces of a dielectric substrate, and the two conductive layers are connected by rows of via-holes that are formed which a spacing that is less than or equal to ½ of the wavelength in the dielectric substrate in the resonance frequency, whereby n stages of dielectric resonators and input/output waveguide structures are formed. If the number n of stages is assumed to be 3, the first-stage resonator and the second-stage resonator are coupled by an electromagnetic field by means of via-holes of a first spacing; the second-stage resonator and the third-stage resonator are coupled by an electromagnetic by means of via-holes of a second spacing, whereby a filter is formed. The input/output waveguide structure and the filter are coupled by an electromagnetic by means of via-holes of a fourth spacing. The first-stage resonator and the third-stage resonator are coupled by an electromagnetic field by means of via-holes of a third spacing.

TECHNICAL FIELD

The present invention relates to a dielectric waveguide filter that hasan upper conductive layer and a lower conductive layer on the surfacesof a dielectric substrate, wherein a row of via-holes or conductors thatconnect the upper conductive layer and lower conductive layer is used toform resonators and dielectric windows.

BACKGROUND ART

There exists a need for filters that feature low loss and a steepout-of-band suppression characteristic, and further, that featurecompact size and connectability with a planar circuit. From thestandpoint of connection reproducibility and low parasitic inductance athigh frequencies, it is also strongly desired that such filters allowflip-chip packaging. One filter having these characteristics is shown inFIG. 1 and described in the public literature in a paper by M. Ito etal. (IEEE International Microwave Symposium Digest, pp. 1597–1600, May2001). FIG. 1A is a plan view of this known example of a filter, andFIG. 1B is a sectional view taken along alternate long and short dashline E–E′ in FIG. 1A. Conductive layers 2 a and 2 b are formed on theupper and lower surfaces of dielectric substrate 1, and these upper andlower conductive layers 2 a and 2 b are connected by via-hole rows 3 athat are formed such that spacing Ip in the direction of signalpropagation is less than or equal to ½ of the guide wavelength, wherebya waveguide is formed. A waveguide filter is achieved by formingvia-holes 3 b that constitute dielectric windows within this waveguideat spacing I₁, I₂, I₃, I₄ that is equal to or less than ½ of the guidewavelength. In addition, waveguide-coplanar converters 10 are formedover the first-stage and final-stage resonators, thesewaveguide-coplanar converters being connected to input/output coplanarlines that are made up of ground conductive layer 2 a and signalconductive layer 2 c. Finally, to improve the out-of-band suppressioncharacteristic, coplanar resonators 15 that provide a bandwidthelimination characteristic are connected to waveguide-coplanarconverters 10.

When fabricating the filter of the above-described known example using aceramic as the dielectric substrate, via-holes were formed by punchingbefore sintering the green sheet, and a conductive pattern was formedafter sintering. As a result, misregistration between the via-holes andthe conductive pattern tends to occur due to the degree of control ofthe coefficient of contraction during sintering. With the filter of thisknown example, due to a coupling by an electromagnetic field betweencoplanar resonators 15 and the dielectric resonators that constitute thefilter, the filter characteristics are highly sensitive tomisregistration between via-holes 3 a and 3 b and upper conductive layer2 a, as shown in FIG. 6. As a consequence, problems are encountered infabrication such as a high degree of variability in performance and lowyield.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a dielectricwaveguide filter that is capable of forming out-of-band attenuationpoles without additionally forming openings for interlacedelectromagnetic field coupling.

According to a first aspect of the invention, in a dielectric waveguidefilter that has an upper conductive layer and a lower conductive layeron the surfaces of a dielectric substrate, and conductors that connectthe upper conductive layer and the lower conductive layer to form nfilter stages comprising resonators and dielectric windows, the number nof filter stages is 3 or more, and the first to n^(th) resonators aresuccessively coupled by electromagnetic fields and adjacent torespective resonators such that the i^(th) resonator is coupled to thej^(th) resonator by an electromagnetic field, where i. j. and n areintegers such that 1≦i<j≦n and j≠i+1.

By two-dimensionally arranging resonators that are surrounded byvia-holes, out-of-band attenuation poles can be formed withoutadditionally providing openings for interlaced electromagnetic fieldcoupling. As a result, the out-of-band suppression characteristic can beimproved, the number of filter stages can be reduced, and a more compactdevice can be realized.

The formation of waveguide-coplanar converters on the dielectricresonators of the input and output stages of the filter enablesflip-chip packaging. In addition, there is no need for providingopenings on resonators other than the input and output stages, and thisconfiguration is therefore less prone to misregistration between theconductive layers and via-holes during fabrication.

According to an embodiment of the present invention, resonators areformed by rows of via-holes that connect the upper and lower conductivelayers that are formed on the surfaces of the dielectric substrate, andthe spacing of the via-holes that form the via-hole rows is less than orequal to ½ of the guide wavelength of the resonance frequency.

According to an embodiment of the present invention, planar lines madeup of slots are formed on the upper conductive layer and/or the lowerconductive layer on the surfaces of the dielectric substrate.

According to another embodiment of the present invention, the planarlines are coplanar lines made up of two coupled slots.

According to another aspect of the present invention, in a dielectricwaveguide filter that has an upper conductive layer and a lowerconductive layer on the surfaces of a dielectric substrate, and rows ofvia-holes that connect the upper conductive layer and the lowerconductive layer to form resonators and dielectric windows, the spacingof the via-holes that form via-hole rows is equal to or less than ½ thewaveguide wavelength of the resonance frequency, and for at least onevia-hole of the via-hole rows, a slot is formed so as to surround theperiphery of the via-hole in the upper conductive layer and/or the lowerconductive layer, and a conductive tab is used to connect the twoconductive layers with each other across the slot.

According to an embodiment of the present invention, the filter isflip-chip packaged, and conductive tab and bumps that are formed on thesubstrate for flip-chip packaging are used to connect the conductivelayers on both sides across slots that are formed surrounding theperipheries of via-holes.

According to an embodiment of the present invention, the number n offilter stages is 3 or more, and the first to n^(th) resonators aresuccessively coupled by electromagnetic fields such that the i^(th)resonator is coupled to the j^(th) resonator by an electromagneticfield, where j≠i±1.

According to an embodiment of the present invention, planar lines aremade up of slots are formed in the upper conductive layer and/or thelower conductive layer on the surfaces of the dielectric substrate.

According to the embodiment of the present invention, the planar linesare coplanar lines made up of two coupled slots.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the configuration of a waveguide filter of the prior art,FIG. 1A being a plan view of the filter substrate, and FIG. 1B being asectional view taken along alternate long and short dash line E–E′ ofFIG. 1A;

FIG. 2 shows the configuration of a first embodiment according to thepresent invention, FIG. 2A showing a plan view of the filter substrateand FIG. 2B showing a sectional view taken along alternate long andshort dash line A–A′ of FIG. 2A;

FIG. 3 shows the configuration of a second embodiment according to thepresent invention, FIG. 3A showing a plan view of the filter substrate,FIG. 3B showing a detailed view of an inductance regulator, and FIG. 3Cshowing a sectional view taken along alternate long and short dash lineB–B′ of FIG. 3B;

FIG. 4 shows the configuration of a third embodiment according to thepresent invention, FIG. 4A showing a plan view of the filter substrate,and FIG. 4B showing a sectional view taken along alternate long andshort dash line C–C′ of FIG. 4A;

FIG. 5 shows the configuration of a fourth embodiment according to thepresent invention, FIG. 5A showing a plan view of the filter substrate,FIG. 5B showing a detailed view of an inductance regulator, and FIG. 5Cshowing a sectional view taken along alternate long and short dash lineD–D′ of FIG. 5B;

FIG. 6 shows the change in characteristic with respect to themisregistration of via-holes and conductive pattern in the filter of theprior art shown in FIG. 1;

FIG. 7 shows the improvement of the out-of-band suppressioncharacteristic realized by the present invention; and

FIG. 8 shows the change in characteristic with respect tomisregistration between via-holes and conductive pattern in a filter ofthe present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

A first embodiment according to the present invention will now beexplained in detail with reference to FIG. 2. FIG. 2A is a plan view ofa filter substrate, and FIG. 2B is a sectional view taken alongalternate long and short dash line A–A′ in FIG. 2A.

Upper and lower conductive layers 2 a and 2 b are formed on the upperand lower surfaces of dielectric substrate 1. Upper and lower conductivelayers 2 a and 2 b are connected each other by via-hole rows 3 a and 3 bthat are formed with a spacing being equal to or less than ½ of thewavelength in the dielectric substrate at the resonance frequency,whereby first-stage, second-stage, and third-stage dielectric resonators5 a, 5 b, and 5 c and input/output waveguide structures 4 a and 4 b areformed. The filter is configured such that first-stage resonator 5 a andsecond-stage resonator 5 b are coupled by an electromagnetic field bymeans of dielectric windows in the form of via-holes 3 b with a spacingbeing equal to d₁₂ and second-stage resonator 5 b and third-stageresonator 5 c are coupled by an electromagnetic field by means ofdielectric windows in the form of via-holes 3 b with a spacing beingequal to d₂₃. Input/output waveguide structures 4 a and 4 b and thefilter are electromagnetically coupled by dielectric windows in the formof via-holes 3 b with a spacing being equal to d_(I/O). Two-dimentionalarrangement of resonators 5 a, 5 b, and 5 c makes it possible to easilyprovide coupling by an interlaced electromagnetic field betweenfirst-stage resonator 5 a and third-stage resonator 5 c by means ofdielectric windows in the form of via-holes 3 b with a spacing beingequal to d13. This allows to provide an attenuation pole on thehigh-frequency side of the pass band, as shown by the transmissioncharacteristic of the filter in FIG. 7, thus improving the out-of-bandsuppression characteristic. The filter described in the public documentshown in FIG. 1 has openings formed thereon that function as coplanarresonators 15 to introduce attenuation poles on the resonators that formthe filter, but the filter of the present invention lacks theseopenings. Thus, as shown in FIG. 8, change in characteristic resultingfrom misregistration of via-holes 3 a and 3 b with respect to conductivelayer 2 a can be adequately controlled. In addition, the filter of thepresent embodiment can realize coupling by an interlaced electromagneticfield by only the arrangement of via-holes and therefore does notrequire additional fabrication steps.

As a second embodiment of the present invention, a configuration thatallows regulation of the filter characteristics will be explained withreference to FIG. 3. FIG. 3A is a plan view of the filter substrate,FIG. 3B is a detailed view of the area 6 enclosed by the dotted lines inFIG. 3A, and FIG. 3C is a sectional view taken along alternate long andshort dash line B–B′ in FIG. 3B.

Forming slot 7 around the periphery of via-hole 3 a that forms aresonator causes pad 8 to be formed that is electrically isolated fromconductive layer 2 a. This pad 8 and conductive layer 2 a are connectedwith each other by, for example, bonding wires 9. The number of wires ortheir length are regulated to form inductance regulator 6 for regulatingthe inductance of via-holes 3 a that form the side walls of thedielectric resonator. Changes in the inductance change the resonancefrequency of the dielectric resonator. Accordingly, forming inductanceregulator 6 in each resonator stage enables regulation of the centerfrequency of the filter. In addition, forming inductance regulators 6 atvia-holes 3 b that form the dielectric windows enables regulation of thedegree of electromagnetic field coupling between dielectric resonators.In such a case, the bandwidth of the filter can be regulated.

A third embodiment of the present invention will now be explained indetail with reference to FIG. 4. FIG. 4A is a plan view of the filtersubstrate, and FIG. 4B is a sectional view taken along alternate longand short dash line C–C′ in FIG. 4A.

Upper and lower conductive layer 2 a and 2 b are formed on the surfacesof dielectric substrate 1. First-stage, second-stage, and third-stagedielectric resonators 5 a, 5 b, and 5 c are formed by connecting theseupper and lower conductive layers 2 a and 2 b by means of via-hole rows3 a and 3 b that are formed with a spacing being equal to or less than ½of the wavelength in the dielectric substrate at the resonancefrequency. Formed on first-stage resonator 5 a and third-stage resonator5 c are waveguide-coplanar converters 10 that are connected toinput/output coplanar lines that are made up of ground conductive layer2 a and signal conductive layer 2 c. The degree of electromagnetic fieldcoupling between input/output stage resonators 5 a and 5 c andwaveguide-coplanar converters 10 is regulated by the length I_(t) ofwaveguide-coplanar converters 10. The filter is configured such thatfirst-stage resonator 5 a and second-stage resonator 5 b are coupled byan electromagnetic field by means of dielectric windows in the form ofvia-holes 3 b with a spacing being equal to d₁₂, and the electromagneticfield second-stage resonator 5 b and third-stage resonator 5 c arecoupled by dielectric windows in the form of via-holes 3 b with aspacing being equal to d₂₃. The two-dimensional arrangement ofresonators 5 a, 5 b, 5 c makes it possible to provide an interlacedelectromagnetic field coupling between first-stage resonator 5 a andthird-stage resonator 5 c by means of the dielectric windows in the formof via-holes 3 b with a spacing being equal to d₁₃. The provision ofnotches 11 in conductive layer 2 a of the input/output portions enablesa reduction of the emission at the end of the substrate. The adoption ofcoplanar lines for input and output enables integration of planarcircuit such as MMIC (Monolithic Microwave Integrated Circuit) and alsoenables flip-chip packaging.

In this case as well, the use of a configuration that is similar to thesecond embodiment allows regulation of the filter characteristics, andthe adoption of coplanar lines for input and output further facilitatesflip-chip packaging.

As a fourth embodiment of the present invention, a configuration thatregulates filter characteristics using flip-chip packaging, will now beexplained with reference to FIG. 5. FIG. 5A is a plan view of the filtersubstrate, FIG. 5B shows the details of area 6 that is delineated bydotted lines in FIG. 5A, and FIG. 5C is a sectional view taken alongalternate long and short dash line D–D′ in FIG. 5B. For the sake ofillustration, however, flip-chip packaging substrate 12 is not shown inFIGS. 5A and 5B.

Forming slot 7 around the periphery of via-hole 3 a that forms aresonator causes pad 8 to be formed that is electrically isolated fromconductive layer 2 a. This pad 8 and conductive layer 2 a are connectedeach other by way of bump 14 and conductive layer 13 that is formed onflip-chip packaging substrate 12, whereby the same effect as the secondembodiment can be obtained. In addition, this embodiment provides theadditional advantage that the filter characteristics can be adjustedwhen the filter substrate undergoes flip-chip packaging, thuseliminating additional frequency adjustment steps.

Although examples have described in the above-described embodiments inwhich the number of filter stages was three, the number of stages may beincreased to obtain the desired characteristics. In addition, aconfiguration for regulating the inductance of the via-holes can also beapplied to the frequency regulation of a single resonator that is usedin a dielectric resonator/oscillator.

1. A dielectric waveguide filter, comprising: an upper conductive layerand a lower conductive layer on the surfaces of a dielectric substrate;and conductors for connecting said upper conductive layer and said lowerconductive layer to form a number, n, of filter stages comprisingresonators and dielectric windows; wherein the number, n, of filterstages is 3 or more, and first to n^(th) resonators are successivelycoupled by electromagnetic fields and are also adjacent to respectiveresonators such that an i^(th) resonator is coupled by anelectromagnetic field to a j^(th) resonator by a window coupling similarto said coupling between through said dielectric windows said resonatorswhich are successively coupled, where 1≦i<j≦n and j≠i+1, wherein saidresonators are formed by via-hole rows that connect said upperconductive layer and said lower conductive layer, and the spacing ofvia-holes that form the via-hole rows is less than or equal to ½ theguide wavelength of the resonance frequency.
 2. A filter according toclaim 1, wherein planar lines made up of slots are formed on said upperconductive layer and/or said lower conductive layer.
 3. A filteraccording to claim 2, wherein said planar lines are coplanar lines madeup of two coupled slots.
 4. A dielectric waveguide filter, comprising:an upper conductive layer and a lower conductive layer on the surfacesof a dielectric substrate; and rows of via-holes that connect said upperconductive layer and said lower conductive layer to form a number, n, offilter stages comprising resonators and dielectric windows; whereinspacing of the via-holes that form the via-hole rows is less than orequal to ½ the guide wavelength of the resonance frequency, and whereinfor at least one via-hole of the via-hole rows, a pad is formed so as tosurround a periphery of the via-hole in the upper conductive layerand/or the lower conductive layer and to be separated from the upperconductive layer and/or the lower conductive layer by a slot, andwherein a conductive tab is used to connect the upper conductive layerand/or the lower conductive layer with the pad across the slot.
 5. Afilter according to claim 4, wherein said filter undergoes flip-chippackaging, and conductive tabs and bumps that are formed on a dielectricsubstrate for flip-chip packaging are used to connect the upperconductive layer and/or the lower conductive layer with the pad.
 6. Afilter according to claim 4, wherein the number, n, of filter stages is3 or more, and first to n^(th) resonators are successively coupled byelectromagnetic fields and are adjacent to respective resonators suchthat an i^(th) resonator is coupled to a j^(th) resonator by anelectromagnetic field, where 1≦i<j≦n and j≠i+1.
 7. A filter according toclaim 4, wherein planar lines made up of slots are formed in said upperconductive layer and/or said lower conductive layer.
 8. A filteraccording to claim 7, wherein said planar lines are coplanar lines madeup of two coupled slots.